The present invention relates to semiconductor devices and, more particularly, to a semiconductor integrated circuit device to a high packing density having a power supply voltage converting circuit for generating a bias voltage suitably supplied to microfabricated transistors fabricated on the submicron order.
In the field of semiconductor integrated circuit devices integrating transistors such as MOSFETs, the packing density has been increasing year by year. For example, in semiconductor memories, the development of a 4- or 16-Mbit dynamic random access memory (referred to as a "dRAM" hereinafter) is in progress. In such memory s having a very high packing density, the minimum fabrication size of transistors used in memory cells, dummy cells, peripheral drivers (including a sense amplifier), etc. is reduced to less than one micron (i.e., the submicron order). In this case, a large number of transistors (generally several millions of transistors) are formed according to the most advanced micro-patterning techniques.
In a micro-fabricated dRAM, channel lengths of MOSFETs constituting its internal circuits are decreased. In this case, when a d.c. power supply voltage of normal level (e.g., 5 volts) is applied to the dRAM, basic characteristics such as operational reliability of each MOSFET and the dielectric strength of the source-drain path thereof are undesirably degraded. This is because an electric field in each micro-fabricated FET on the submicron order is too strong. More specifically, when the channel length of the transistors is decreased, the internal electric field generated in the transistor is increased upon application of a voltage to the source-drain path. As a result, when a normal MOS structure is simply micronized, the dielectric breakdown strength in the source-drain path is abruptly decreased, thereby degrading the operational relability of the semiconductor memory.
In a conventional memory, in order to solve the above problem, a voltage converting circuit is arranged in a highly-integrated IC device to supply a low and constant power supply voltage to transistors microfabricated on the submicron order and constituting its internal circuits. The voltage converting circuit includes a constant voltage circuit for receiving external power supply voltage Vcc (e.g., 5 volts) of the existing standards (the external power supply voltage is set according to the conventional manner so as to establish versatility) and for generating a d.c. voltage Va (e.g., 3 to 4 volts) reduced as an internal power supply voltage. In the conventional voltage converting circuit, when an externally-supplied d.c. voltage is increased and the power supply voltage for internal circuits (i.e., internal power supply voltage) reaches predetermined potential Va, an output voltage of the voltage converting circuit is fixed. Even if the reference d.c. voltage is further increased, the output voltage of the voltage converting circuit is constantly maintained at voltage level Va. Therefore, a proper, low power supply voltage can be stably supplied to the IC internal circuits.
According to ICs incorporating such power supply voltage converting circuits, however, an accelerated test for testing operational reliability of ICs cannot be effectively performed due to the following reason. In such a test, a power supply voltage higher than the normal voltage level must be forcibly applied to the internal circuits. In other words, in order to confirm long-term operational reliability of ICs in a short period of time, a d.c. voltage higher than the normal power supply voltage Vcc by a few volts must be applied to the ICs, and normal operation under such severe conditions must be confirmed. In this case, since the circuit for generating the constant voltage is incorporated in each IC, a prescribed low d.c. voltage is automatically supplied to the internal circuits by the behavior of the power supply voltage converting circuit even if the high voltage for the accelerated test is applied thereto. As a result, such a high voltage cannot be directly applied to the internal circuits, and the accelerated test cannot be performed.
In order to overcome this problem, the characteristics of the constant voltage generator may be modified as follows. Second reference level Vb higher than the reference level by a few volts is set. When the external d.c. power supply voltage applied to the ICs exceeds the second reference voltage, the generator generates a voltage proportional to the external voltage. In other words, constant voltage generation action is limited within the range between first and second reference voltages Va and Vb (Va&lt;Vb). When the external d.c. power supply voltage applied to the ICs is lower than the first reference voltage or higher than the second reference voltage, the voltage changing in proportion to the magnitude of the external power supply voltage is supplied to the internal IC. Therefore, if the accelerated-test voltage is set to be high enough to exceed the second reference level, the accelerated test can be performed. In the normal operation, if the voltage applied to the internal IC is set within the range between voltages Va and Vb, constant voltage generation action in the normal operation mode can be assured. With this arrangement, however, the margin for stably supplying the power supply voltage to the internal IC is undesirably narrowed, which entails another decisive drawback.